library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity error_block is
	port (
		clk : in std_logic;
		reset : in std_logic;
		i_read : in std_logic;
		error : in std_logic;
		sel : out std_logic
	);
end entity;

architecture behavioral of error_block is
type t_state is (NORMAL, ERROR_REQUEST, ERROR_INJECTED);

signal state : t_state;
signal aux_sel : std_logic;
	begin
	
	P1 : process (reset, clk)
	begin
		if reset = '0' then
			state <= NORMAL;
			aux_sel <= '0';
		elsif clk'event and clk = '1' then
			case state is
				when NORMAL =>
					if error = '1' then
						state <= NORMAL;
						aux_sel <= '0';
					else
						state <= ERROR_REQUEST;
						aux_sel <= '0';
					end if;
				when ERROR_REQUEST =>
					if i_read = '1' then
						state <= ERROR_INJECTED;
						aux_sel <= '1';
					else
						state <= ERROR_REQUEST;
						aux_sel <= '0';
					end if;
				when ERROR_INJECTED =>
					if error = '1' then
						state <= NORMAL;
						aux_sel <= '0';
					else
						state <= ERROR_INJECTED;
						aux_sel <= '0';
					end if;
			end case;
		end if;
	end process;
	
	sel <= aux_sel;

end behavioral;